I am a second-year Ph.D. student at Arizona State University, where I am fortunate to be advised by Prof. Vidya A Chhabria. Currently, my research is centered around sustainable computing and chiplet-based heterogeneous integration architecture. I also actively work with Prof. Aman Arora.
I received my Bachelor’s in Electronics and Telecommunication Engineering from R.V. College of Engineering, I then graduated with a Master’s in Electrical Engineering from Arizona State University.
I have a strong interest in fitness, and in my leisure time, I engage in long-distance running.
The smartphone industry’s push for smaller, energy-efficient devices with advanced features often overlooks environmental impacts. Corporate sustainability reports provide broad overviews, masking critical details, especially about carbon footprints (CFP) of components like processors. This paper examines the gap between reported CFP trends and the rising CFP contributions of processors, highlighting deficiencies in reporting practices. We propose specific metrics to improve transparency and guide chip design and manufacturing toward sustainable solutions.
Tool to evaluate the carbon footprint of FPGA-based computing across its lifetime. The tool can also perform comparisons with ASIC counterpart considering differnt aspects such as manufacturing, recycling, disposal, reconfigurability (reuse), operation and design. The sustainable benifits of FPGA compared to ASIC is shown in this work.
Carbon footprint estimator for heterogenous chiplet-based systems. ECO-CHIP is an analysis tool that analyzes the operational and embodied CFP (design, manufacturing, and packaging). The tool supports the following HI and packaging architectures- RDL fanout, silicon bridge-based, passive and active interposer, and 3D integration. The tool evaluates the crucial package/assembly carbon emissions essential for HI systems, considering size, yield, and assembly process. In addition, it also estimates design CFP.